review-wave-6 — the wave-6 gate passes, engine-mem.md flipped to stable

The born-pinned gate audited the mem engine against the contract and
ADR-024: the conformance read clean in mechanism substance (queue
state machine, scheduler collapse, outbox, streams, locks, clock,
validation, tx overlay, wake substrate — incl. a full guard-order and
panic-hygiene audit); the suite's third column read row-by-row and
25/25 green under the per-test current-thread flavor (24 engine-shared
rows + mem's payload_too_large non-occurrence arm + the factory-shape
test); three-way arithmetic equivalence green on all columns; the
wasm32 acceptance items verified (compile-clean, tokio sync+time,
no blocking, flavor enforced); the rider's two arms verified (Finding
1 discharged; Findings 2-3 stay parked for wave 7); workspace gates,
taskgraph validate green.

Three edge-domain fixes landed inline: the stream cursor read's
i64::MAX overflow (Bound::Excluded), trim_to's i64::MAX horizon
endpoint (Bound::Included), and the scheduler register path now
rejecting a parseable interval whose first boundary overflows with
InvalidSpec — the one engine-vs-engine divergence the read found,
aligned into the class-1 window — plus a pinning test and scaffold-
residue doc/comment cleanups (clock allows, tx per-stream wake
comment, wakes/stream module docs). Recorded findings with
dispositions in the task's Notes for the wave-7 pre-release pass:
the multi-thread publish-to-wake ordering tolerance, the heartbeat/
save_offset/EventReceiver-try_recv ADR-023 §2 classification gaps,
and the mem arithmetic being a suite-pinned transplant.

Verified: cargo build; cargo test --workspace green (mem 101 lib +
25 suite, sqlite 191+25, pg 124+25+9 server-less, core 25, harness 3);
clippy --all-targets -D warnings clean; fmt clean; taskgraph validate
(61 tasks). Gate record: tasks/review-wave-6.md (Notes + Summary),
implementation.md wave-6 row + review-rounds entry.

docs/architecture/engine-mem.md

@@ -1,9 +1,13 @@
 ---
-status: implementation-complete
-last_updated: 2026-10-10 (the wave-6 wave landed: the full surface
-wired over guarded state, the suite's third `StoreFactory` column
-green on the host under the current-thread flavor, the wasm32
-compile gate clean — the review gate holds the stable flip)
+status: stable
+last_updated: 2026-10-10 (the wave-6 review gate passed: the
+conformance read clean — three edge-domain fixes landed inline (the
+stream cursor read's `i64::MAX` overflow, `trim_to`'s horizon
+endpoint, the scheduler register-time interval overflow now rejecting
+with `InvalidSpec` like the SQLite register) plus scaffold-residue
+cleanup; the third column's 25-row set green under the current-thread
+flavor; the wasm32 gate + feature subset verified; the rider's arms
+verified)
 ---
 
 # Mem engine

docs/plans/implementation.md

@@ -1,11 +1,10 @@
 ---
 status: draft
-last_updated: 2026-10-10 (ADR-024 — the mem engine adopted as wave 6,
-release readiness renumbered to wave 7; wave 6 decomposed — eleven
-tasks per the pg-wave rhythm with the tx overlay load-bearing. Waves
-1–5 implemented and reviewed; engine specs stable. Wave-5 review
-residue decomposed — pg-fix-scheduler-fire-wake; flake-watch carried
-to wave 7.)
+last_updated: 2026-10-10 (wave 6 implemented and reviewed — the mem
+engine landed, the suite's third column green under the current-thread
+flavor, the wasm32 gate clean, the wave-6 gate passed with three
+inline edge-domain fixes; Findings 2–3 and the flake watch carry to
+wave 7.)
 ---
 
 # alkstore — Implementation plan
@@ -44,7 +43,7 @@ core crate plus the finished suite (wave 5) — born pinned, per
 | [3](#wave-3--sqlite-engine) | SQLite engine: connection architecture, re-derived queue ops on contract v1, scheduler/outbox, tx seam, SQLite backlog column | waves 1 + 2 | implemented + reviewed (2026-10-08) |
 | 4 | [Postgres engine](#wave-4--postgres-engine): schema bootstrap, pool/open, listener/forwarder, all mechanisms, tx seam, pg backlog column | wave 1 | implemented + reviewed (2026-10-08) |
 | 5 | [Contract suite](#wave-5--contract-suite): the cross-engine equivalence properties (core-contract.md §Verification backlog), version-stamped per ADR-017 | waves 3 + 4 | implemented + reviewed (2026-10-10) |
-| 6 | [Mem engine](#wave-6--mem-engine): separate `alkstore-mem` crate, full contract v1 over in-memory mechanisms (tx overlay, queue/scheduler/streams/locks/wakes), the suite's third factory column (born pinned), wasm32 compile-clean acceptance | waves 1 + 5 | decomposed (2026-10-10) |
+| 6 | [Mem engine](#wave-6--mem-engine): separate `alkstore-mem` crate, full contract v1 over in-memory mechanisms (tx overlay, queue/scheduler/streams/locks/wakes), the suite's third factory column (born pinned), wasm32 compile-clean acceptance | waves 1 + 5 | implemented + reviewed (2026-10-10) |
 | 7 | [Release readiness](#wave-7--release-readiness): crate docs, deployment matrix final pass, README (written last, honestly), publish prep; fuzzing decision | wave 6 | not yet decomposed |
 
 ## Wave 1 — Foundations
@@ -496,7 +495,34 @@ decomposes. Specific gates:
   structural twin; wave-3 outcomes absorbed (constructors exist;
   arithmetic re-owned per engine; per-engine `@every` parser;
   SQLite-scoped deferred notes stay put). See the Wave 4 section.
-- **Wave 6 decomposition** (2026-10-10) — ADR-024 adopted the mem
+- **Wave 6 review gate** (`review-wave-6`, 2026-10-10) — the
+  born-pinned gate passed: the conformance read clean (queue state
+  machine, scheduler collapse, outbox, streams, locks, clock,
+  validation, tx overlay, wake substrate each verified against the
+  contract and the pinned ADRs; guard-order discipline audited across
+  every section-guard site); the suite's third column read row-by-row
+  and green (the 24 engine-shared rows + mem's
+  `payload_too_large_never_produced_on_mem` arm + the factory-shape
+  test, 25 green under the per-test current-thread flavor);
+  three-way arithmetic equivalence green (backoff curve, opts
+  resolution on all three columns); the wasm32 acceptance items
+  verified (compile-clean, tokio sync+time subset, no blocking calls,
+  flavor enforced); the rider's arms verified (Finding 1 discharged;
+  Findings 2–3 confirmed still parked for wave 7). Three edge-domain
+  fixes landed inline at the gate: the stream cursor read's `i64::MAX`
+  overflow (`Bound::Excluded`), `trim_to`'s `i64::MAX` horizon
+  endpoint (`Bound::Included`), and the scheduler register path
+  aligning with SQLite on rejecting a parseable interval whose first
+  boundary overflows (`InvalidSpec`). Unpinned contract-adjacent
+  observations recorded in the task's Notes for the wave-7 pre-release
+  pass: the multi-thread publish-to-wake ordering tolerance (same
+  shape implied for the SQL engines; nothing pins wake-fire order vs
+  offset order), the `heartbeat(extend)`/`save_offset`/
+  `EventReceiver::try_recv`-closed classifications missing from the
+  ADR-023 §2 table, and the mem arithmetic being a transplant of the
+  SQLite implementations (equivalence suite-pinned; ownership letter
+  satisfied). `engine-mem.md` flipped to `stable`.
+- **Wave-6 decomposition** (2026-10-10) — ADR-024 adopted the mem
   engine the same day the wave-5 gate closed; the task set follows the
   pg wave's rhythm with the tx overlay as the load-bearing task, the
   suite's third column as the born-pinned deliverable, the harness's